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<DIV id="content" class="Child" onclick="hideTocList()"><PRE>
<A name="timing_rpt_top">Timing Report</A><B><U><big></big></U></B>
Lattice Timing Report -  Setup  and Hold, Version Radiant Software (64-bit) 2.0.0.64.1

Wed Sep 23 23:41:30 2020

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2019 Lattice Semiconductor Corporation,  All rights reserved.

Command line:    timing -sethld -v 10 -u 10 -endpoints 10 -nperend 1 -html -rpt fft_adc_impl_1.tws fft_adc_impl_1_syn.udb -gui

-----------------------------------------
Design:          top
Family:          iCE40UP
Device:          iCE40UP5K
Package:         SG48
Performance:     High-Performance_1.2V
-----------------------------------------


=====================================================================
                    Table of Contents
=====================================================================
<LI>    <A href=#Timing_rpt_DesignChecking>1  DESIGN CHECKING</A></LI>
<LI>        <A href=#Timing_rpt_SDCConstraints>1.1  SDC Constraints</A></LI>
<LI>        <A href=#Timing_rpt_CombinationalLoop>1.2  Combinational Loop</A></LI>
<LI>    <A href=#Timing_rpt_ClockSummary>2  CLOCK SUMMARY</A></LI>
<LI>        <A href=#Timing_rpt_Clk_1>2.1  Clock ADC_REF_CLK_c</A></LI>
<LI>        <A href=#Timing_rpt_Clk_2>2.2  Clock pll_adc_inst/lscc_pll_inst/clk</A></LI>
<LI>    <A href=#Timing_rpt_AnalysisSummary>3  TIMING ANALYSIS SUMMARY</A></LI>
<LI>        <A href=#Timing_rpt_Overall>3.1  Overall (Setup and Hold)</A></LI>
<LI>            <A href=#Timing_rpt_ConstraintCoverage>3.1.1  Constraint Coverage</A></LI>
<LI>            <A href=#Timing_rpt_Errors>3.1.2  Timing Errors</A></LI>
<LI>            <A href=#Timing_rpt_TotalScore>3.1.3  Total Timing Score</A></LI>
<LI>        <A href=#Timing_rpt_SetupSummary>3.2  Setup Summary Report</A></LI>
<LI>        <A href=#Timing_rpt_HoldSummary>3.3  Hold Summary Report</A></LI>
<LI>        <A href=#Timing_rpt_UnconstrainedReport>3.4  Unconstrained Report</A></LI>
<LI>            <A href=#Timing_rpt_UnconstrainedEndpoints>3.4.1  Unconstrained Start/End Points</A></LI>
<LI>            <A href=#Timing_rpt_StartEndPointsWithoutTimingConstraints>3.4.2  Start/End Points Without Timing Constraints</A></LI>
<LI>    <A href=#Timing_rpt_DetailedReport>4  DETAILED REPORT</A></LI>
<LI>        <A href=#Timing_rpt_SetupDetailedReport>4.1  Setup Detailed Report</A></LI>
<LI>        <A href=#Timing_rpt_HoldDetailedReport>4.2  Hold Detailed Report</A></LI>

=====================================================================
                    End of Table of Contents
=====================================================================


<A name="Timing_rpt_DesignChecking"></A><B><U><big>1  DESIGN CHECKING</big></U></B>

<A name="Timing_rpt_SDCConstraints"></A><B><U><big>1.1  SDC Constraints</big></U></B>

create_generated_clock -name {ADC_REF_CLK_c} -source [get_pins {pll_adc_inst/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 64 -divide_by 48 [get_pins {pll_adc_inst/lscc_pll_inst/u_PLL_B/OUTCORE }] 
create_clock -name {pll_adc_inst/lscc_pll_inst/clk} -period 20.83333333 [get_nets clk]

<A name="Timing_rpt_CombinationalLoop"></A><B><U><big>1.2  Combinational Loop</big></U></B>


<A name="Timing_rpt_ClockSummary"></A><B><U><big>2  CLOCK SUMMARY</big></U></B>

<A name="Timing_rpt_Clk_1"></A><B><U><big>2.1 Clock "ADC_REF_CLK_c"</big></U></B>

create_generated_clock -name {ADC_REF_CLK_c} -source [get_pins {pll_adc_inst/lscc_pll_inst/u_PLL_B/REFERENCECLK}] -multiply_by 64 -divide_by 48 [get_pins {pll_adc_inst/lscc_pll_inst/u_PLL_B/OUTCORE }] 

Single Clock Domain
-------------------------------------------------------------------------------------------------------
          Clock ADC_REF_CLK_c           |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From ADC_REF_CLK_c                     |             Target |          15.384 ns |         65.003 MHz 
                                        | Actual (all paths) |               ---- |               ---- 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
          Clock ADC_REF_CLK_c           |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From pll_adc_inst/lscc_pll_inst/clk    |                         ---- |                      No path 
------------------------------------------------------------------------------------------------------
<A name="Timing_rpt_Clk_2"></A><B><U><big>2.2 Clock "pll_adc_inst/lscc_pll_inst/clk"</big></U></B>

create_clock -name {pll_adc_inst/lscc_pll_inst/clk} -period 20.83333333 [get_nets clk]

Single Clock Domain
-------------------------------------------------------------------------------------------------------
  Clock pll_adc_inst/lscc_pll_inst/clk  |                    |       Period       |     Frequency      
-------------------------------------------------------------------------------------------------------
 From pll_adc_inst/lscc_pll_inst/clk    |             Target |          20.833 ns |         48.001 MHz 
                                        | Actual (all paths) |          20.830 ns |         48.008 MHz 
-------------------------------------------------------------------------------------------------------

Clock Domain Crossing
------------------------------------------------------------------------------------------------------
  Clock pll_adc_inst/lscc_pll_inst/clk  |   Worst Time Between Edges   |           Comment            
------------------------------------------------------------------------------------------------------
 From ADC_REF_CLK_c                     |                         ---- |                      No path 
------------------------------------------------------------------------------------------------------


<A name="Timing_rpt_AnalysisSummary"></A><B><U><big>3  TIMING ANALYSIS SUMMARY</big></U></B>

<A name="Timing_rpt_Overall"></A><B><U><big>3.1  Overall (Setup and Hold)</big></U></B>

<A name="Timing_rpt_ConstraintCoverage"></A><B><U><big>3.1.1  Constraint Coverage</big></U></B>

Constraint Coverage: 0.304151%

<A name="Timing_rpt_Errors"></A><B><U><big>3.1.2  Timing Errors</big></U></B>

Timing Errors: 0 endpoints (setup), 0 endpoints (hold)

<A name="Timing_rpt_TotalScore"></A><B><U><big>3.1.3  Total Timing Score</big></U></B>

Total Negative Slack: 0.000 ns (setup), 0.000 ns (hold)

<A name="Timing_rpt_SetupSummary"></A><B><U><big>3.2  Setup Summary Report</big></U></B>

-------------------------------------------------------
          Listing 10 End Points          |    Slack    
-------------------------------------------------------
reset_rep_1557/D                         |   11.307 ns 
reset/D                                  |   11.307 ns 
reset_cnt_777_778__i6/SP                 |   13.859 ns 
reset_cnt_777_778__i6/D                  |   13.859 ns 
reset_cnt_777_778__i5/SP                 |   13.859 ns 
reset_cnt_777_778__i5/D                  |   13.859 ns 
reset_cnt_777_778__i4/SP                 |   13.859 ns 
reset_cnt_777_778__i3/SP                 |   13.859 ns 
reset_cnt_777_778__i2/SP                 |   13.859 ns 
reset_cnt_777_778__i1/SP                 |   13.859 ns 
-------------------------------------------------------
                                         |             
Setup # of endpoints with negative slack:|           0 
                                         |             
-------------------------------------------------------

<A name="Timing_rpt_HoldSummary"></A><B><U><big>3.3  Hold Summary Report</big></U></B>

-------------------------------------------------------
          Listing 10 End Points          |    Slack    
-------------------------------------------------------
reset_cnt_777_778__i5/SP                 |    4.196 ns 
reset_cnt_777_778__i5/D                  |    4.196 ns 
reset_cnt_777_778__i4/SP                 |    4.196 ns 
reset_cnt_777_778__i4/D                  |    4.196 ns 
reset_cnt_777_778__i3/SP                 |    4.196 ns 
reset_cnt_777_778__i3/D                  |    4.196 ns 
reset_cnt_777_778__i2/SP                 |    4.196 ns 
reset_cnt_777_778__i2/D                  |    4.196 ns 
reset_cnt_777_778__i1/SP                 |    4.196 ns 
reset_cnt_777_778__i1/D                  |    4.196 ns 
-------------------------------------------------------
                                         |             
Hold # of endpoints with negative slack: |           0 
                                         |             
-------------------------------------------------------

<A name="Timing_rpt_UnconstrainedReport"></A><B><U><big>3.4  Unconstrained Report</big></U></B>

<A name="Timing_rpt_UnconstrainedEndpoints"></A><B><U><big>3.4.1  Unconstrained Start/End Points</big></U></B>

Clocked but unconstrained timing start points
-------------------------------------------------------------------
         Listing 2 Start Points         |           Type           
-------------------------------------------------------------------
reset/Q                                 |          No required time
reset_rep_1557/Q                        |          No required time
-------------------------------------------------------------------
                                        |                          
Number of unconstrained timing start po |                          
ints                                    |                         2
                                        |                          
-------------------------------------------------------------------

Clocked but unconstrained timing end points
-------------------------------------------------------------------
         Listing 10 End Points          |           Type           
-------------------------------------------------------------------
fifo_i2s/lscc_fifo_inst/wr_addr_r_i0/D  |    No arrival or required
fifo_i2s/lscc_fifo_inst/full_r_c/D      |    No arrival or required
fifo_i2s/lscc_fifo_inst/full_mem_r_c/D  |    No arrival or required
fifo_i2s/lscc_fifo_inst/empty_ext_r/D   |    No arrival or required
fifo_i2s/lscc_fifo_inst/empty_r_c/D     |    No arrival or required
fifo_i2s/lscc_fifo_inst/empty_mem_r_c/D |    No arrival or required
fifo_i2s/lscc_fifo_inst/wr_addr_p1_r_i0/D                           
                                        |    No arrival or required
fifo_i2s/lscc_fifo_inst/wr_cmpaddr_r_i0/D                           
                                        |    No arrival or required
fifo_i2s/lscc_fifo_inst/wr_addr_p1cmp_r_i1/D                           
                                        |    No arrival or required
fifo_i2s/lscc_fifo_inst/waddr_r_i0/D    |    No arrival or required
-------------------------------------------------------------------
                                        |                          
Number of unconstrained timing end poin |                          
ts                                      |                      3715
                                        |                          
-------------------------------------------------------------------

<A name="Timing_rpt_StartEndPointsWithoutTimingConstraints"></A><B><U><big>3.4.2  Start/End Points Without Timing Constraints</big></U></B>

I/O ports without constraint
----------------------------
Possible constraints to use on I/O ports are:
set_input_delay,
set_output_delay,
set_max_delay,
create_clock,
create_generated_clock,
...

-------------------------------------------------------------------
     Listing 10 Start or End Points     |           Type           
-------------------------------------------------------------------
BUT_USER                                |                     input
BUT_TRIG                                |                     input
PHV                                     |                    output
PnHV                                    |                    output
PDamp                                   |                    output
HILO                                    |                    output
HV_EN                                   |                    output
ADC_REF_CLK                             |                    output
LED_R                                   |                    output
LED_G                                   |                    output
-------------------------------------------------------------------
                                        |                          
Number of I/O ports without constraint  |                        17
                                        |                          
-------------------------------------------------------------------

Registers without clock definition
Define the clock for these registers.
-------------------------------------------------------------------
         Listing 10 Instance(s)         |           Type           
-------------------------------------------------------------------
spi_strb_adc_clk_zzz_c                  |                  No Clock
spi_strb_adc_clk_zzzz_c                 |                  No Clock
spi_data_byte_c                         |                  No Clock
dac_mem_data_wr_i0_i0                   |                  No Clock
regs[3][31]                             |                  No Clock
regs[3][30]                             |                  No Clock
spi_strb_adc_clk_z_c                    |                  No Clock
spi_strb_adc_clk_zz_c                   |                  No Clock
regs[3][29]                             |                  No Clock
regs[3][28]                             |                  No Clock
-------------------------------------------------------------------
                                        |                          
Number of registers without clock defin |                          
ition                                   |                      2086
                                        |                          
-------------------------------------------------------------------

<A name="Timing_rpt_DetailedReport"></A><B><U><big>4  DETAILED REPORT</big></U></B>
<A name="Timing_rpt_SetupDetailedReport"></A><B><U><big>4.1  Setup Detailed Report</big></U></B>


XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Detail report of critical paths

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
                    Detailed Report for timing paths 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i1/Q  (FD1P3XZ)
Path End         : reset_rep_1557/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 4
Delay Ratio      : 69.7% (route), 30.3% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 11.307 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/CK",
        "phy_name":"reset_cnt_777_778__i1/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


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    "path_end":
    {
        "type":"pin",
        "log_name":"reset_rep_1557/D",
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    "path_sections":[
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            "phy_name":"reset_cnt[0]"
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        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
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            "log_name":"i1_2_lut_3_lut_adj_38407/C",
            "phy_name":"i1_2_lut_3_lut_adj_38407/C"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_3_lut_adj_38407/Z",
            "phy_name":"i1_2_lut_3_lut_adj_38407/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n6_adj_5521",
            "phy_name":"n6_adj_5521"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i4_4_lut/D",
            "phy_name":"i4_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i4_4_lut/Z",
            "phy_name":"i4_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_N_341[0]",
            "phy_name":"reset_N_341[0]"
        },
        "arrive":8.850,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i4_4_lut_lut_buf_1/A",
            "phy_name":"i4_4_lut_lut_buf_1/A"
        },
        "pin1":
        {
            "log_name":"i4_4_lut_lut_buf_1/Z",
            "phy_name":"i4_4_lut_lut_buf_1/Z"
        },
        "arrive":9.327,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44881",
            "phy_name":"n44881"
        },
        "arrive":11.402,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i1/CK->reset_cnt_777_778__i1/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[0]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_3_lut_adj_38407/C->i1_2_lut_3_lut_adj_38407/Z
                                          LUT4            C_TO_Z_DELAY   0.477         4.223  1       
n6_adj_5521                                               NET DELAY      2.075         6.298  1       
i4_4_lut/D->i4_4_lut/Z                    LUT4            D_TO_Z_DELAY   0.477         6.775  1       
reset_N_341[0]                                            NET DELAY      2.075         8.850  1       
i4_4_lut_lut_buf_1/A->i4_4_lut_lut_buf_1/Z
                                          LUT4            A_TO_Z_DELAY   0.477         9.327  2       
n44881 ( D )                                              NET DELAY      2.075        11.402  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_rep_1557/CK",
        "phy_name":"reset_rep_1557/CK"
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            "phy_name":""
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        "arrive":20.833,
        "delay":0.000
    },
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            "phy_name":"clk"
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        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                         -11.402  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  11.307  




++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i1/Q  (FD1P3XZ)
Path End         : reset/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 4
Delay Ratio      : 69.7% (route), 30.3% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 11.307 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/CK",
        "phy_name":"reset_cnt_777_778__i1/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/Q",
        "phy_name":"reset_cnt_777_778__i1/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset/D",
        "phy_name":"reset/D"
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    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
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            "log_name":"reset_cnt_777_778__i1/CK",
            "phy_name":"reset_cnt_777_778__i1/CK"
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            "log_name":"reset_cnt_777_778__i1/Q",
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        "arrive":3.466,
        "delay":1.391
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    {
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            "log_name":"reset_cnt[0]",
            "phy_name":"reset_cnt[0]"
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        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i1_2_lut_3_lut_adj_38407/C",
            "phy_name":"i1_2_lut_3_lut_adj_38407/C"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_3_lut_adj_38407/Z",
            "phy_name":"i1_2_lut_3_lut_adj_38407/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n6_adj_5521",
            "phy_name":"n6_adj_5521"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i4_4_lut/D",
            "phy_name":"i4_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i4_4_lut/Z",
            "phy_name":"i4_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_N_341[0]",
            "phy_name":"reset_N_341[0]"
        },
        "arrive":8.850,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i4_4_lut_lut_buf_1/A",
            "phy_name":"i4_4_lut_lut_buf_1/A"
        },
        "pin1":
        {
            "log_name":"i4_4_lut_lut_buf_1/Z",
            "phy_name":"i4_4_lut_lut_buf_1/Z"
        },
        "arrive":9.327,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44881",
            "phy_name":"n44881"
        },
        "arrive":11.402,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i1/CK->reset_cnt_777_778__i1/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[0]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_3_lut_adj_38407/C->i1_2_lut_3_lut_adj_38407/Z
                                          LUT4            C_TO_Z_DELAY   0.477         4.223  1       
n6_adj_5521                                               NET DELAY      2.075         6.298  1       
i4_4_lut/D->i4_4_lut/Z                    LUT4            D_TO_Z_DELAY   0.477         6.775  1       
reset_N_341[0]                                            NET DELAY      2.075         8.850  1       
i4_4_lut_lut_buf_1/A->i4_4_lut_lut_buf_1/Z
                                          LUT4            A_TO_Z_DELAY   0.477         9.327  2       
n44881 ( D )                                              NET DELAY      2.075        11.402  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset/CK",
        "phy_name":"reset/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                         -11.402  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  11.307  




++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i4/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i6/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/Q",
        "phy_name":"reset_cnt_777_778__i4/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i6/SP",
        "phy_name":"reset_cnt_777_778__i6/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i4/CK",
            "phy_name":"reset_cnt_777_778__i4/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i4/Q",
            "phy_name":"reset_cnt_777_778__i4/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[3]",
            "phy_name":"reset_cnt[3]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i1_2_lut_rep_1524/B",
            "phy_name":"i1_2_lut_rep_1524/B"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_rep_1524/Z",
            "phy_name":"i1_2_lut_rep_1524/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44841",
            "phy_name":"n44841"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/D",
            "phy_name":"i36249_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i4/CK->reset_cnt_777_778__i4/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  5       
reset_cnt[3]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_rep_1524/B->i1_2_lut_rep_1524/Z  LUT4            B_TO_Z_DELAY   0.477         4.223  1       
n44841                                                    NET DELAY      2.075         6.298  1       
i36249_4_lut/D->i36249_4_lut/Z            LUT4            D_TO_Z_DELAY   0.477         6.775  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i6/CK",
        "phy_name":"reset_cnt_777_778__i6/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  




++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i3/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i6/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/CK",
        "phy_name":"reset_cnt_777_778__i3/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/Q",
        "phy_name":"reset_cnt_777_778__i3/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i6/D",
        "phy_name":"reset_cnt_777_778__i6/D"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i3/CK",
            "phy_name":"reset_cnt_777_778__i3/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i3/Q",
            "phy_name":"reset_cnt_777_778__i3/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[2]",
            "phy_name":"reset_cnt[2]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27804_2_lut_rep_1353_3_lut/C",
            "phy_name":"i27804_2_lut_rep_1353_3_lut/C"
        },
        "pin1":
        {
            "log_name":"i27804_2_lut_rep_1353_3_lut/Z",
            "phy_name":"i27804_2_lut_rep_1353_3_lut/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44670",
            "phy_name":"n44670"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27822_3_lut_4_lut/B",
            "phy_name":"i27822_3_lut_4_lut/B"
        },
        "pin1":
        {
            "log_name":"i27822_3_lut_4_lut/Z",
            "phy_name":"i27822_3_lut_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n30",
            "phy_name":"n30"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i3/CK->reset_cnt_777_778__i3/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  6       
reset_cnt[2]                                              NET DELAY      0.280         3.746  1       
i27804_2_lut_rep_1353_3_lut/C->i27804_2_lut_rep_1353_3_lut/Z
                                          LUT4            C_TO_Z_DELAY   0.477         4.223  1       
n44670                                                    NET DELAY      2.075         6.298  1       
i27822_3_lut_4_lut/B->i27822_3_lut_4_lut/Z
                                          LUT4            B_TO_Z_DELAY   0.477         6.775  1       
n30 ( D )                                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i6/CK",
        "phy_name":"reset_cnt_777_778__i6/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  




++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i4/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i5/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/Q",
        "phy_name":"reset_cnt_777_778__i4/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/SP",
        "phy_name":"reset_cnt_777_778__i5/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i4/CK",
            "phy_name":"reset_cnt_777_778__i4/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i4/Q",
            "phy_name":"reset_cnt_777_778__i4/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[3]",
            "phy_name":"reset_cnt[3]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i1_2_lut_rep_1524/B",
            "phy_name":"i1_2_lut_rep_1524/B"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_rep_1524/Z",
            "phy_name":"i1_2_lut_rep_1524/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44841",
            "phy_name":"n44841"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/D",
            "phy_name":"i36249_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i4/CK->reset_cnt_777_778__i4/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  5       
reset_cnt[3]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_rep_1524/B->i1_2_lut_rep_1524/Z  LUT4            B_TO_Z_DELAY   0.477         4.223  1       
n44841                                                    NET DELAY      2.075         6.298  1       
i36249_4_lut/D->i36249_4_lut/Z            LUT4            D_TO_Z_DELAY   0.477         6.775  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/CK",
        "phy_name":"reset_cnt_777_778__i5/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  




++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i1/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i5/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/CK",
        "phy_name":"reset_cnt_777_778__i1/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/Q",
        "phy_name":"reset_cnt_777_778__i1/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/D",
        "phy_name":"reset_cnt_777_778__i5/D"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i1/CK",
            "phy_name":"reset_cnt_777_778__i1/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i1/Q",
            "phy_name":"reset_cnt_777_778__i1/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[0]",
            "phy_name":"reset_cnt[0]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27797_2_lut_rep_1441/B",
            "phy_name":"i27797_2_lut_rep_1441/B"
        },
        "pin1":
        {
            "log_name":"i27797_2_lut_rep_1441/Z",
            "phy_name":"i27797_2_lut_rep_1441/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44758",
            "phy_name":"n44758"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27815_2_lut_3_lut_4_lut/B",
            "phy_name":"i27815_2_lut_3_lut_4_lut/B"
        },
        "pin1":
        {
            "log_name":"i27815_2_lut_3_lut_4_lut/Z",
            "phy_name":"i27815_2_lut_3_lut_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n31",
            "phy_name":"n31"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i1/CK->reset_cnt_777_778__i1/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[0]                                              NET DELAY      0.280         3.746  1       
i27797_2_lut_rep_1441/B->i27797_2_lut_rep_1441/Z
                                          LUT4            B_TO_Z_DELAY   0.477         4.223  1       
n44758                                                    NET DELAY      2.075         6.298  1       
i27815_2_lut_3_lut_4_lut/B->i27815_2_lut_3_lut_4_lut/Z
                                          LUT4            B_TO_Z_DELAY   0.477         6.775  1       
n31 ( D )                                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/CK",
        "phy_name":"reset_cnt_777_778__i5/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  




++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i4/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i4/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/Q",
        "phy_name":"reset_cnt_777_778__i4/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/SP",
        "phy_name":"reset_cnt_777_778__i4/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i4/CK",
            "phy_name":"reset_cnt_777_778__i4/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i4/Q",
            "phy_name":"reset_cnt_777_778__i4/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[3]",
            "phy_name":"reset_cnt[3]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i1_2_lut_rep_1524/B",
            "phy_name":"i1_2_lut_rep_1524/B"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_rep_1524/Z",
            "phy_name":"i1_2_lut_rep_1524/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44841",
            "phy_name":"n44841"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/D",
            "phy_name":"i36249_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i4/CK->reset_cnt_777_778__i4/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  5       
reset_cnt[3]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_rep_1524/B->i1_2_lut_rep_1524/Z  LUT4            B_TO_Z_DELAY   0.477         4.223  1       
n44841                                                    NET DELAY      2.075         6.298  1       
i36249_4_lut/D->i36249_4_lut/Z            LUT4            D_TO_Z_DELAY   0.477         6.775  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk                                                       NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  




++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i4/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i3/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/Q",
        "phy_name":"reset_cnt_777_778__i4/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/SP",
        "phy_name":"reset_cnt_777_778__i3/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i4/CK",
            "phy_name":"reset_cnt_777_778__i4/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i4/Q",
            "phy_name":"reset_cnt_777_778__i4/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[3]",
            "phy_name":"reset_cnt[3]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i1_2_lut_rep_1524/B",
            "phy_name":"i1_2_lut_rep_1524/B"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_rep_1524/Z",
            "phy_name":"i1_2_lut_rep_1524/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44841",
            "phy_name":"n44841"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/D",
            "phy_name":"i36249_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i4/CK->reset_cnt_777_778__i4/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  5       
reset_cnt[3]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_rep_1524/B->i1_2_lut_rep_1524/Z  LUT4            B_TO_Z_DELAY   0.477         4.223  1       
n44841                                                    NET DELAY      2.075         6.298  1       
i36249_4_lut/D->i36249_4_lut/Z            LUT4            D_TO_Z_DELAY   0.477         6.775  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/CK",
        "phy_name":"reset_cnt_777_778__i3/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  




++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i4/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i2/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/Q",
        "phy_name":"reset_cnt_777_778__i4/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/SP",
        "phy_name":"reset_cnt_777_778__i2/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i4/CK",
            "phy_name":"reset_cnt_777_778__i4/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i4/Q",
            "phy_name":"reset_cnt_777_778__i4/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[3]",
            "phy_name":"reset_cnt[3]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i1_2_lut_rep_1524/B",
            "phy_name":"i1_2_lut_rep_1524/B"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_rep_1524/Z",
            "phy_name":"i1_2_lut_rep_1524/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44841",
            "phy_name":"n44841"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/D",
            "phy_name":"i36249_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i4/CK->reset_cnt_777_778__i4/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  5       
reset_cnt[3]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_rep_1524/B->i1_2_lut_rep_1524/Z  LUT4            B_TO_Z_DELAY   0.477         4.223  1       
n44841                                                    NET DELAY      2.075         6.298  1       
i36249_4_lut/D->i36249_4_lut/Z            LUT4            D_TO_Z_DELAY   0.477         6.775  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  




++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i4/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i1/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 3
Delay Ratio      : 65.4% (route), 34.6% (logic)
Clock Skew       : 0.000 ns
Setup Constraint : 20.833 ns 
Path Slack       : 13.859 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/Q",
        "phy_name":"reset_cnt_777_778__i4/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/SP",
        "phy_name":"reset_cnt_777_778__i1/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i4/CK",
            "phy_name":"reset_cnt_777_778__i4/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i4/Q",
            "phy_name":"reset_cnt_777_778__i4/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[3]",
            "phy_name":"reset_cnt[3]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i1_2_lut_rep_1524/B",
            "phy_name":"i1_2_lut_rep_1524/B"
        },
        "pin1":
        {
            "log_name":"i1_2_lut_rep_1524/Z",
            "phy_name":"i1_2_lut_rep_1524/Z"
        },
        "arrive":4.223,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n44841",
            "phy_name":"n44841"
        },
        "arrive":6.298,
        "delay":2.075
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/D",
            "phy_name":"i36249_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":6.775,
        "delay":0.477
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":8.850,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i4/CK->reset_cnt_777_778__i4/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  5       
reset_cnt[3]                                              NET DELAY      0.280         3.746  1       
i1_2_lut_rep_1524/B->i1_2_lut_rep_1524/Z  LUT4            B_TO_Z_DELAY   0.477         4.223  1       
n44841                                                    NET DELAY      2.075         6.298  1       
i36249_4_lut/D->i36249_4_lut/Z            LUT4            D_TO_Z_DELAY   0.477         6.775  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         8.850  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/CK",
        "phy_name":"reset_cnt_777_778__i1/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":20.833,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":22.908,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000        20.833  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000        20.833  9       
clk ( CK )                                                NET DELAY      2.075        22.908  1       
                                                          Uncertainty    0.000        22.908  
                                                          Setup time     0.199        22.709  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         22.709  
Arrival Time                                                                          -8.850  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                  13.859  



+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
                    End of Detailed Report for timing paths 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 


##########################################################

<A name="Timing_rpt_HoldDetailedReport"></A><B><U><big>4.2  Hold Detailed Report</big></U></B>


XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Detail report of critical paths

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
                    Detailed Report for timing paths 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i2/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i5/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/Q",
        "phy_name":"reset_cnt_777_778__i2/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/SP",
        "phy_name":"reset_cnt_777_778__i5/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i2/CK",
            "phy_name":"reset_cnt_777_778__i2/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i2/Q",
            "phy_name":"reset_cnt_777_778__i2/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[1]",
            "phy_name":"reset_cnt[1]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/C",
            "phy_name":"i36249_4_lut/C"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i2/CK->reset_cnt_777_778__i2/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[1]                                              NET DELAY      0.280         3.746  1       
i36249_4_lut/C->i36249_4_lut/Z            LUT4            C_TO_Z_DELAY   0.450         4.196  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/CK",
        "phy_name":"reset_cnt_777_778__i5/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk ( CK )                                                NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 2 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i4/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i5/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/Q",
        "phy_name":"reset_cnt_777_778__i4/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/D",
        "phy_name":"reset_cnt_777_778__i5/D"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i4/CK",
            "phy_name":"reset_cnt_777_778__i4/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i4/Q",
            "phy_name":"reset_cnt_777_778__i4/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[3]",
            "phy_name":"reset_cnt[3]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27815_2_lut_3_lut_4_lut/D",
            "phy_name":"i27815_2_lut_3_lut_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i27815_2_lut_3_lut_4_lut/Z",
            "phy_name":"i27815_2_lut_3_lut_4_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n31",
            "phy_name":"n31"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i4/CK->reset_cnt_777_778__i4/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  5       
reset_cnt[3]                                              NET DELAY      0.280         3.746  1       
i27815_2_lut_3_lut_4_lut/D->i27815_2_lut_3_lut_4_lut/Z
                                          LUT4            D_TO_Z_DELAY   0.450         4.196  1       
n31 ( D )                                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i5/CK",
        "phy_name":"reset_cnt_777_778__i5/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk ( CK )                                                NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 3 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i2/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i4/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/Q",
        "phy_name":"reset_cnt_777_778__i2/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/SP",
        "phy_name":"reset_cnt_777_778__i4/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i2/CK",
            "phy_name":"reset_cnt_777_778__i2/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i2/Q",
            "phy_name":"reset_cnt_777_778__i2/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[1]",
            "phy_name":"reset_cnt[1]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/C",
            "phy_name":"i36249_4_lut/C"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i2/CK->reset_cnt_777_778__i2/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[1]                                              NET DELAY      0.280         3.746  1       
i36249_4_lut/C->i36249_4_lut/Z            LUT4            C_TO_Z_DELAY   0.450         4.196  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk ( CK )                                                NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 4 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i3/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i4/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/CK",
        "phy_name":"reset_cnt_777_778__i3/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/Q",
        "phy_name":"reset_cnt_777_778__i3/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/D",
        "phy_name":"reset_cnt_777_778__i4/D"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i3/CK",
            "phy_name":"reset_cnt_777_778__i3/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i3/Q",
            "phy_name":"reset_cnt_777_778__i3/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[2]",
            "phy_name":"reset_cnt[2]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27808_2_lut_3_lut_4_lut/D",
            "phy_name":"i27808_2_lut_3_lut_4_lut/D"
        },
        "pin1":
        {
            "log_name":"i27808_2_lut_3_lut_4_lut/Z",
            "phy_name":"i27808_2_lut_3_lut_4_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n32",
            "phy_name":"n32"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i3/CK->reset_cnt_777_778__i3/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  6       
reset_cnt[2]                                              NET DELAY      0.280         3.746  1       
i27808_2_lut_3_lut_4_lut/D->i27808_2_lut_3_lut_4_lut/Z
                                          LUT4            D_TO_Z_DELAY   0.450         4.196  1       
n32 ( D )                                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i4/CK",
        "phy_name":"reset_cnt_777_778__i4/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk ( CK )                                                NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 5 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i2/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i3/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/Q",
        "phy_name":"reset_cnt_777_778__i2/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/SP",
        "phy_name":"reset_cnt_777_778__i3/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i2/CK",
            "phy_name":"reset_cnt_777_778__i2/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i2/Q",
            "phy_name":"reset_cnt_777_778__i2/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[1]",
            "phy_name":"reset_cnt[1]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/C",
            "phy_name":"i36249_4_lut/C"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i2/CK->reset_cnt_777_778__i2/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[1]                                              NET DELAY      0.280         3.746  1       
i36249_4_lut/C->i36249_4_lut/Z            LUT4            C_TO_Z_DELAY   0.450         4.196  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/CK",
        "phy_name":"reset_cnt_777_778__i3/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk ( CK )                                                NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 6 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i3/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i3/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/CK",
        "phy_name":"reset_cnt_777_778__i3/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/Q",
        "phy_name":"reset_cnt_777_778__i3/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/D",
        "phy_name":"reset_cnt_777_778__i3/D"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i3/CK",
            "phy_name":"reset_cnt_777_778__i3/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i3/Q",
            "phy_name":"reset_cnt_777_778__i3/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[2]",
            "phy_name":"reset_cnt[2]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27801_2_lut_3_lut/C",
            "phy_name":"i27801_2_lut_3_lut/C"
        },
        "pin1":
        {
            "log_name":"i27801_2_lut_3_lut/Z",
            "phy_name":"i27801_2_lut_3_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n33",
            "phy_name":"n33"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i3/CK->reset_cnt_777_778__i3/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  6       
reset_cnt[2]                                              NET DELAY      0.280         3.746  1       
i27801_2_lut_3_lut/C->i27801_2_lut_3_lut/Z
                                          LUT4            C_TO_Z_DELAY   0.450         4.196  1       
n33 ( D )                                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i3/CK",
        "phy_name":"reset_cnt_777_778__i3/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 7 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i2/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i2/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/Q",
        "phy_name":"reset_cnt_777_778__i2/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/SP",
        "phy_name":"reset_cnt_777_778__i2/SP"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i2/CK",
            "phy_name":"reset_cnt_777_778__i2/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i2/Q",
            "phy_name":"reset_cnt_777_778__i2/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[1]",
            "phy_name":"reset_cnt[1]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/C",
            "phy_name":"i36249_4_lut/C"
        },
        "pin1":
        {
            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i2/CK->reset_cnt_777_778__i2/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[1]                                              NET DELAY      0.280         3.746  1       
i36249_4_lut/C->i36249_4_lut/Z            LUT4            C_TO_Z_DELAY   0.450         4.196  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 8 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i1/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i2/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/CK",
        "phy_name":"reset_cnt_777_778__i1/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/Q",
        "phy_name":"reset_cnt_777_778__i1/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/D",
        "phy_name":"reset_cnt_777_778__i2/D"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i1/CK",
            "phy_name":"reset_cnt_777_778__i1/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i1/Q",
            "phy_name":"reset_cnt_777_778__i1/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[0]",
            "phy_name":"reset_cnt[0]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27794_2_lut/B",
            "phy_name":"i27794_2_lut/B"
        },
        "pin1":
        {
            "log_name":"i27794_2_lut/Z",
            "phy_name":"i27794_2_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n34_2",
            "phy_name":"n34_2"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i1/CK->reset_cnt_777_778__i1/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[0]                                              NET DELAY      0.280         3.746  1       
i27794_2_lut/B->i27794_2_lut/Z            LUT4            B_TO_Z_DELAY   0.450         4.196  1       
n34_2 ( D )                                               NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
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            "log_name":"",
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        },
        "pin1":
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            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk ( CK )                                                NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 9 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i2/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i1/SP  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/CK",
        "phy_name":"reset_cnt_777_778__i2/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
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            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
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    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i2/Q",
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        "log_name":"reset_cnt_777_778__i1/SP",
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        "pin1":
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            "log_name":"reset_cnt_777_778__i2/Q",
            "phy_name":"reset_cnt_777_778__i2/Q"
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        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[1]",
            "phy_name":"reset_cnt[1]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i36249_4_lut/C",
            "phy_name":"i36249_4_lut/C"
        },
        "pin1":
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            "log_name":"i36249_4_lut/Z",
            "phy_name":"i36249_4_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt_7__N_505",
            "phy_name":"reset_cnt_7__N_505"
        },
        "arrive":6.271,
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    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i2/CK->reset_cnt_777_778__i2/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[1]                                              NET DELAY      0.280         3.746  1       
i36249_4_lut/C->i36249_4_lut/Z            LUT4            C_TO_Z_DELAY   0.450         4.196  6       
reset_cnt_7__N_505 ( SP )                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
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        "arrive":0.000,
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    }
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</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk ( CK )                                                NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  




++++ Path 10 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 

Path Begin       : reset_cnt_777_778__i1/Q  (FD1P3XZ)
Path End         : reset_cnt_777_778__i1/D  (FD1P3XZ)
Source Clock     : pll_adc_inst/lscc_pll_inst/clk
Destination Clock: pll_adc_inst/lscc_pll_inst/clk
Logic Level      : 2
Delay Ratio      : 56.1% (route), 43.9% (logic)
Clock Skew       : 0.000 ns
Hold Constraint  : 0.000 ns 
Path Slack       : 4.196 ns  (Passed)

<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/CK",
        "phy_name":"reset_cnt_777_778__i1/CK"
    },
    "path_sections":[
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
        "arrive":2.075,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>
Name                                      Cell/Site Name  Delay Name     Delay  Arrival Time  Fanout  
----------------------------------------  --------------  -------------  -----  ------------  ------  
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/Q",
        "phy_name":"reset_cnt_777_778__i1/Q"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/D",
        "phy_name":"reset_cnt_777_778__i1/D"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"reset_cnt_777_778__i1/CK",
            "phy_name":"reset_cnt_777_778__i1/CK"
        },
        "pin1":
        {
            "log_name":"reset_cnt_777_778__i1/Q",
            "phy_name":"reset_cnt_777_778__i1/Q"
        },
        "arrive":3.466,
        "delay":1.391
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"reset_cnt[0]",
            "phy_name":"reset_cnt[0]"
        },
        "arrive":3.746,
        "delay":0.280
    },
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"i27792_1_lut/A",
            "phy_name":"i27792_1_lut/A"
        },
        "pin1":
        {
            "log_name":"i27792_1_lut/Z",
            "phy_name":"i27792_1_lut/Z"
        },
        "arrive":4.196,
        "delay":0.450
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"n35",
            "phy_name":"n35"
        },
        "arrive":6.271,
        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

reset_cnt_777_778__i1/CK->reset_cnt_777_778__i1/Q
                                          FD1P3XZ         CK_TO_Q_DELAY  1.391         3.466  7       
reset_cnt[0]                                              NET DELAY      0.280         3.746  1       
i27792_1_lut/A->i27792_1_lut/Z            LUT4            A_TO_Z_DELAY   0.450         4.196  1       
n35 ( D )                                                 NET DELAY      2.075         6.271  1       


<tapath class="path_info">
<xmp>
{
    "path_begin":
    {
        "type":"pin",
        "log_name":"hi_clock_gen_inst/CLKHF",
        "phy_name":"hi_clock_gen_inst/CLKHF"
    },
    "path_end":
    {
        "type":"pin",
        "log_name":"reset_cnt_777_778__i1/CK",
        "phy_name":"reset_cnt_777_778__i1/CK"
    },
    "path_sections":[
    {
        "type":"site_delay",
        "pin0":
        {
            "log_name":"",
            "phy_name":""
        },
        "pin1":
        {
            "log_name":"",
            "phy_name":""
        },
        "arrive":0.000,
        "delay":0.000
    },
    {
        "type":"net_delay",
        "net":
        {
            "log_name":"clk",
            "phy_name":"clk"
        },
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        "delay":2.075
    }
    ]
}
</xmp>
</tapath>

                                                          CONSTRAINT     0.000         0.000  1       
hi_clock_gen_inst/CLKHF                   HSOSC_CORE      CLOCK LATENCY  0.000         0.000  9       
clk                                                       NET DELAY      2.075         2.075  1       
                                                          Uncertainty    0.000         2.075  
                                                          Hold time      0.000         2.075  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Required Time                                                                         -2.075  
Arrival Time                                                                           6.271  
----------------------------------------  --------------  -------------  -----  ------------  ------  
Path Slack  (Passed)                                                                   4.196  



+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
                    End of Detailed Report for timing paths 
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 


##########################################################






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</PRE></DIV>

<DIV id="toc" class="radiant"<span onmousemove="showTocList()">Contents</span>
<UL id="toc_list">
<LI><A href=#timing_rpt_top>Timing Report</A></LI>
<LI><A href=#Timing_rpt_DesignChecking>1  DESIGN CHECKING</A></LI>
<UL>
<LI><A href=#Timing_rpt_SDCConstraints>1.1  SDC Constraints</A></LI>
<LI><A href=#Timing_rpt_CombinationalLoop>1.2  Combinational Loop</A></LI>
</UL>
<LI><A href=#Timing_rpt_ClockSummary>2  CLOCK SUMMARY</A></LI>
<LI><A href=#Timing_rpt_AnalysisSummary>3  TIMING ANALYSIS SUMMARY</A></LI>
<UL>
<LI><A href=#Timing_rpt_Overall>3.1  Overall (Setup and Hold)</A></LI>
<LI><A href=#Timing_rpt_SetupSummary>3.2  Setup Summary Report</A></LI>
<LI><A href=#Timing_rpt_HoldSummary>3.3  Hold Summary Report</A></LI>
<LI><A href=#Timing_rpt_UnconstrainedReport>3.4  Unconstrained Report</A></LI>
</UL>
<LI><A href=#Timing_rpt_DetailedReport>4  DETAILED REPORT</A></LI>
<UL>
<LI><A href=#Timing_rpt_SetupDetailedReport>4.1  Setup Detailed Report</A></LI>
<LI><A href=#Timing_rpt_HoldDetailedReport>4.2  Hold Detailed Report</A></LI>
</UL>
</UL>
</DIV>

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